The present invention generally relates to 3D semiconductor packaging, and more particularly to improving the dimensional stability of a laminate structure.
Current semiconductor integrated circuit packaging technologies may use flip chip plastic ball grid array (FCPBGA) laminate substrates to form a grid array of pads on which solder balls may be placed to provide electrical connections to the laminate. Most of these FCPBGA laminate structures may utilize a fiberglass reinforced epoxy core, upon which thin dielectric layers are added and metalized to allow for complex semiconductor wiring from the chip to a printed circuit board.
Over time, the mechanically stabilizing core thickness has been reduced, allowing for improved electrical performance including, for example, reduced inductance and improved power distribution resulting from finer plated-through holes (PTH) ground rules. However, an increase in laminate warpage has been observed, impacting bond and assembly yields. Warpage may include undesired deformations of the laminate substrate caused mainly due to stress induced by aggressive thermal treatments.
In order to minimize the aforementioned problems, coreless laminates may provide a practical alternative. One of the advantages of coreless laminates is that they do not have the limitations of cored laminate structures for conducting wiring through the epoxy core, and thus, take advantage of the resulting higher wiring densities enabled at all levels of the coreless laminates. Consequently, coreless laminates having equivalent electrical function with fewer layers may be produced. However, a trade-off of coreless laminates may be the mechanical integrity of their structure which may make handling a challenging task during both laminate fabrication and subsequent module assembly levels.